By Topic

A single-chip 802.11a MAC/PHY with a 32 b RISC processor

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

16 Author(s)
T. Fujisawa ; Toshiba Corp. Semicond., Kawasaki, Japan ; J. Hasegawa ; K. Tsuchie ; T. Shiozawa
more authors

An 802.11a compliant MAC/PHY processing chip has been successfully fabricated in 0.18 /spl mu/m CMOS. Thirty million transistors are integrated on a 10.91 /spl times/ 10.91 mm/sup 2/ die in a 361-pin PFBGA. The MAC functions are fully implemented by firmware on an embedded 32 b RISC processor and hardware acceleration logic. The PHY supports a complete set of data rates up to 54 Mb/s.

Published in:

Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC. 2003 IEEE International

Date of Conference:

13-13 Feb. 2003