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A second-order semi-digital clock recovery circuit based on injection locking

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9 Author(s)
Lee, M.-J.E. ; Velio Commun., Milpitas, CA, USA ; Dally, W.J. ; Poulton, J. ; Greer, T.
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A 3.125Gb/s clock recovery circuit in 0.18/spl mu/m CMOS comprises a multiplying delay-locked loop (MDLL), an injection-locked slave oscillator and a phase control unit. Injection locking reduces MDLL clock distortion and varies the delay of the recovered clock, while a frequency loop in the phase control unit ameliorates the trade off between phase wander and frequency tolerance. Experimental results show high frequency jitter tolerance is improved by 0.08UI.

Published in:

Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC. 2003 IEEE International

Date of Conference:

13-13 Feb. 2003