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A 10Gb/s/ch 50mW 120/spl times/130/spl mu/m/sup 2/ clock and data recovery circuit

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2 Author(s)
Kaeriyama, S. ; NEC, Sagamihara, Japan ; Mizuno, M.

A 10Gb/s clock and data recovery circuit for SerDes macro uses half the power and a quarter the die size of prior art. In 0.15/spl mu/m CMOS the CDR dissipates 50mW in an area of 120/spl times/130/spl mu/m/sup 2/ while maintaining a 10Gb/s bandwidth per channel. Jitter tolerance is also improved and the influence of PVT variations is reduced.

Published in:

Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC. 2003 IEEE International

Date of Conference:

13-13 Feb. 2003