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A passive switched-capacitor /spl Sigma//spl Delta/ ADC consisting of only switches, capacitors and a comparator, is implemented in a 0.13/spl mu/m digital CMOS process. This high-speed low-voltage architecture is used in a zero-IF GSM transceiver and has a measured peak SNDR of 67dB over a bandwidth of 100kHz with a SFDR of 75dB and a dynamic range of 72dB. The ADC consumes 1mA from a 1.5V power supply at a clock rate of 104MHz.
Date of Conference: 13-13 Feb. 2003