By Topic

Noise analysis of correlated double sampling SC integrators with a hold capacitor

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

1 Author(s)
O. Oliaei ; Motorola Labs., Schaumburg, IL, USA

Noise performance of the correlated double sampling switched-capacitor integrators incorporating a supplementary hold capacitor is analyzed. These types of integrators rely on an extra capacitor to attenuate the amplifier low-frequency noise. Approximate expressions for the input-referred noise of the integrators are derived. It is shown that a large parasitic capacitance at the amplifier input may seriously degrade the low-frequency noise performance of such structures.

Published in:

IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications  (Volume:50 ,  Issue: 9 )