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In multilevel IC manufacturing, it's important to have a planar surface preceding the next layer to avoid topographical margin issues. To achieve the local, as well as global, planarity of the wafer surface many innovative technologies have been developed. The development of Chemical-Mechanical Polishing (CMP) has led to dramatic improvement in planarity of dielectrics and later in the development of planar plug-fill and dual damascene copper metallization. It is well known that CMP causes dishing of a layer to be planarized due to uneven distribution of device structures and thus reducing the effectiveness of this technology. One of the solutions for this dishing phenomenon has been the introduction of pattern fill methodology to improve the planarity of a given layer. However, dummy pattern adds capacitive load and thus, parasitic effects on both analog and digital circuits. In this paper a unique fill methodology is presented that reduces the impact on parasitic capacitance while improving the dielectric planarity through the use of irregularly shaped fill features and restrictions to placement of these features.
Date of Conference: 30 June-2 July 2003