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Optimization of Bosch etch process for through wafer interconnects

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3 Author(s)
L. Kenoyer ; Coll. of Eng., Boise State Univ., ID, USA ; R. Oxford ; A. Moll

The Bosch etch process was utilized to create 50 micrometer vias with an aspect ration of 10:1 in silicon wafers for through wafer interconnects. The process is complex with twenty-two separate parameters required to control the process. Deviating from the standard process and flowing SF6 during the deposition process resulted in a more stable and reproducible process.

Published in:

University/Government/Industry Microelectronics Symposium, 2003. Proceedings of the 15th Biennial

Date of Conference:

30 June-2 July 2003