By Topic

Automatic layout generation for CMOS operational amplifiers

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

3 Author(s)
Koh Han Young ; Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA ; Sequin, C.H. ; Gray, P.R.

An analog silicon compiler for CMOS op amps (OPASYN) has been developed. The synthesis system takes as inputs system-level specifications, fabrication-dependent technology parameters, and geometric layout rules. Based on the general domain of the specifications, the program first selects an appropriate circuit topology from a database and determines optimal values for the set of design parameters so as to meet the design objectives. Subsequently, a mask-level layout for the given circuit with its optimized device sizes is constructed using an approach based on a few leaf-cell generators and on circuit-dependent slicing trees that guarantee sound arrangements of the individual components. The synthesis process is fast enough for the program to be used interactively at the system-design level by system engineers who are inexperienced in op amp design.<>

Published in:

Computer-Aided Design, 1988. ICCAD-88. Digest of Technical Papers., IEEE International Conference on

Date of Conference:

7-10 Nov. 1988