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A new layout optimization methodology for CMOS complex gates

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2 Author(s)
Chen, C.Y.R. ; Dept. of Electr. & Comput. Eng., Syracuse Univ., NY, USA ; Hou, C.Y.

Efficient algorithms for the layout generation of CMOS complex gates are presented. Heuristics which use the concept of delayed binding are introduced. An optimized net list is decided during the layout generation phase, rather than before. Examples are given showing that this approach can achieve a considerable improvement over previous ones.<>

Published in:

Computer-Aided Design, 1988. ICCAD-88. Digest of Technical Papers., IEEE International Conference on

Date of Conference:

7-10 Nov. 1988

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