Skip to Main Content
For high bandwidth and low stand-by power DDR (Double Data Rate) I/O interface, a new fully analog DLL (Delay Locked Loop) are designed and implemented in 0.16 /spl mu/m DRAM process. Utilizing a tracking ADC (Analog-to-Digital Converter), a large stand-by current of the analog DLL is suppressed without losing locking information nor compromising jitter performance. Two-step duty correction scheme using multiphase clocks and phase mixing corrects an inherent duty-error of a system clock with more precision and speed, especially for a large duty-error. Proposed DLL has a 100 MHz/spl sim/520 MHz wide lock-range and a 65 psec peak-to-peak jitter and 0.064 psec/mv supply sensitivity at 2.3 v supply voltage consuming 1.1 mA of stand-by current.