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Accurate integrity assessment of on-chip interconnect temperature rise is essential for high performance chip design. This paper presents a compact analytical model for estimating the temperature rise of multilevel ULSI interconnects incorporating via effect. The predicted temperature distributions are shown to be in excellent agreement with the 3-D finite element thermal simulation (ANSYS) results. Additionally, this model provides an efficient approach to analyze realistic chip level interconnect temperature which is extremely difficult to do with ANSYS. Significant difference in temperature distribution and maximum temperature rise is observed between the realistic situation of heat dissipation with vias and the overly simplified case that ignores via effect. The closed-form expression is further applied to evaluate the impact of the interconnect heating on the various design rule parameters and scaling of deep sub-micron Cu/low-k interconnects.