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A 40-GHz frequency divider in 0.18-/spl mu/m CMOS technology

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2 Author(s)
Jri Lee ; Electr. Eng. Dept., California Univ., Los Angeles, CA, USA ; Razavi, B.

A frequency divider employs resonance techniques by means of on-chip spiral inductors to operate at high speeds. Configured as two cascaded /spl divide/2 stages, the circuit achieves a frequency range of 2.3 GHz at 40 GHz while consuming 31 mW from a 2.5-V supply.

Published in:

VLSI Circuits, 2003. Digest of Technical Papers. 2003 Symposium on

Date of Conference:

12-14 June 2003