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A 90 nm 1 GHz 22 mW 16/spl times/16-bit 2's complement multiplier for wireless baseband

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5 Author(s)
Zeydel, B.R. ; Dept. of ECE, California Univ., Davis, CA, USA ; Oklobdzija, V.G. ; Mathew, S. ; Krishnamurthy, R.K.
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This paper describes a static 16/spl times/16-bit 2's complement wireless baseband multiplier testchip in 1.2 V, 90 nm dual-Vt CMOS technology. One-hot Booth encoding, sum/delay difference optimized 3:2 compressor tree, and signal-profile optimized final adder schemes are employed to achieve 1 GHz, 22 mW operation at 1.2 V, scalable to 500 MHz, 3 mW at 0.8 V.

Published in:

VLSI Circuits, 2003. Digest of Technical Papers. 2003 Symposium on

Date of Conference:

12-14 June 2003