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10 GHz, 20 mW, fast locking, adaptive gain PLLs with on-chip frequency calibration for agile frequency synthesis in a 0.18 /spl mu/m digital CMOS process

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6 Author(s)
Ravi, A. ; Commun. & Interconnect Technol., Intel Corp., Hillsboro, OR, USA ; Banerjee, G. ; Bishop, R.E. ; Bloechel, B.A.
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This paper describes two fully integrated 10 GHz PLLs with an LC-VCO implemented in a 0.18 /spl mu/m native digital CMOS process. In the first version, an adaptive gain circuit along with a wide-swing charge pump improves the lock range and ensures faster settling. The PLL has a 1.6 GHz tuning range, a 0.5 /spl mu/s settling time (for a frequency step equal to 10% of the tuning range), reference sideband power of -58 dBc and phase noise of -105 dBc/Hz at a 10 kHz offset and -120 dBc/Hz at a 20 MHz offset (rms jitter of 1.3 ps) while dissipating less than 20 mW from a 1.6 V power supply. Enhancing the process with deep n-wells appears to improve the noise isolation of the circuit by about 5 dB. The second variant incorporates a combination of coarse and fine tuning for the VCO along with a new frequency calibration circuit based on a digital quadri-correlator. This PLL has a 1.25 GHz tuning range, a 10 /spl mu/s settling time, a reference sideband power below the noise floor and a phase noise of -105 dBc/Hz at 10 kHz and -130 dBc/Hz at 20 MHz from the carrier (rms jitter of 1.2 ps).

Published in:

VLSI Circuits, 2003. Digest of Technical Papers. 2003 Symposium on

Date of Conference:

12-14 June 2003