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Low jitter Butterworth delay-locked loops

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3 Author(s)
Hsiang-Hui Chang ; Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan ; Chih-Hao Sun ; Shen-Iuan Liu

The low jitter Butterworth delay-locked loops (DLLs) are presented in this paper. The proposed Butterworth DLLs can suppress both the jitters generated by the input noise and the voltage-controlled delay line (VCDL) noise without stability considerations. Theoretically, the proposed Butterworth 2/sup nd/-order DLL and 3/sup rd/-order one could reduce the rms jitter due to the VCDL by a factor of /spl radic/2 and 2, respectively. In addition, a technique called dynamic bandwidth-adjusting scheme (DBAS) is adopted to shorten the lock time without compromising the jitter performance. The conventional DLL and the proposed ones are simultaneously fabricated at the same die in a CMOS 0.35-um one-poly four-metal process. Compared with the conventional DLL, the measured rms jitters of the proposed DLLs can be improved by a factor of 1.40 and 1.95, respectively, with an input frequency of 125 MHz. The maximum power consumption of the proposed DLLs is 32 mW.

Published in:

VLSI Circuits, 2003. Digest of Technical Papers. 2003 Symposium on

Date of Conference:

12-14 June 2003