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A 27-mW 3.6-Gb/s I/O transceiver

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4 Author(s)
K. L. J. Wong ; California Univ., Los Angeles, CA, USA ; M. Mansuri ; H. Hatamkhani ; C. -K. K. Y. Yang

This paper describes a 3.6-Gbps 27-mW transceiver for chip-to-chip applications. A novel data receiving and timing recovery technique are presented with very low power penalties while maintaining high signal integrity. The input comparator filters noise with built-in bandwidth control and digital offset compensation while consuming 300 uW. Static phase offset introduced onto the charge-pump permits phase recovery with no additional power. The entire design occupies 0.2 mm/sup 2/ in a 0.18-/spl mu/m 1.8-V CMOS technology.

Published in:

VLSI Circuits, 2003. Digest of Technical Papers. 2003 Symposium on

Date of Conference:

12-14 June 2003