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A memory using one-transistor gain cell on SOI(FBC) with performance suitable for embedded DRAM's

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13 Author(s)
T. Ohsawa ; SoC Res. & Dev. Center, Toshiba Corp., Yokohama, Japan ; T. Higashi ; K. Fujita ; T. Ikehashi
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A 288 Kbit memory chip featuring a one-transistor gain cell on SOI of the size 0.21 /spl mu/m/sup 2/(7F/sup 2/ with F=0.175 /spl mu/m) which we named the floating body transistor cell (FBC) is presented and basic characteristics of the cell and the memory chip performance are disclosed. The threshold voltages of a cell transistor in the chip for the data "1" and for the data "0" are measured by using a direct access test circuit and a fail bit map for the 96 Kbit array is obtained. A sensing scheme which was designed to eliminate the effect of cell characteristics variation due to process and temperature fluctuation as common mode noise is verified to be working and the random access time is measured to be less than 100 ns. The characteristics of data hold demonstrate that the FBC can satisfy retention time specifications for some embedded memories. The access time and the data retention time show that the FBC has a potential to be used as a future embedded DRAM memory cell.

Published in:

VLSI Circuits, 2003. Digest of Technical Papers. 2003 Symposium on

Date of Conference:

12-14 June 2003