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A 50-mW/ch 2.5-Gb/s/ch data recovery circuit for the SFI-5 interface using novel eye-tracking method

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6 Author(s)
Saito, T. ; Central Res. Lab., Hitachi Ltd., Tokyo, Japan ; Yamashita, H. ; Yuki, F. ; Baba, T.
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We developed a 2.5-Gb/s/ch digital data recovery (DR) circuit for the SFI-5 interface. Our unique approach of treating a sequential 16-bit incoming data as one unit achieved a fully digital "eye-tracking" DR circuit. Fabricated by 0.18-/spl mu/m SiGe-BiCMOS technology, the area of the DR circuit is 0.02-mm/sup 2//ch and its power consumption is 50 mW/ch at 1.8 V. The measured jitter tolerance at 2.5 Gb/s is 0.7 UI p-p, which satisfies the jitter specifications for the SFI-5.

Published in:

VLSI Circuits, 2003. Digest of Technical Papers. 2003 Symposium on

Date of Conference:

12-14 June 2003