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A design for digital, dynamic clock deskew

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4 Author(s)
C. E. Dike ; Intel Corp., Hillsboro, OR, USA ; N. A. Kurd ; P. Patra ; J. Barkatullah

Unintentional clock skews between clock domains represent an increasing and costly overhead in high-performance VLSI chips. We describe a novel yet easy-to-implement design that reduces skew between local clock domains dynamically or statically by sensing clock-delay differences and then tuning the clock of each domain relative to its neighbors. Lowering local clock skew is accomplished without compromising worst-case global skew.

Published in:

VLSI Circuits, 2003. Digest of Technical Papers. 2003 Symposium on

Date of Conference:

12-14 June 2003