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Fabrication of high aspect ratio through-wafer vias in CMOS wafers for 3-D packaging applications

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4 Author(s)
F. E. Rasmussen ; MIC, Tech. Univ. Denmark, Lyngby, Denmark ; J. Frech ; M. Heschel ; O. Hansen

A process for fabrication of through-wafer vias in CMOS wafers is presented. The process presented offers simple and well controlled fabrication of through-wafer vias using DRIE formation of wafer through-holes, low temperature deposition of through-hole insulation, doubled sided sputtering of Cr/Au, and electroless deposition of Cu. A novel characteristic of the process is the use of a metal etch stop layer providing perfect control of the etch profile of the wafer through-holes in combination with a remarkably improved etch uniformity across the wafer. Excellent through-hole insulation is provided through the use of a CVD deposited polymer, Parylene C, whereas electroless deposition of Cu ensures even distribution of the via metallization.

Published in:

TRANSDUCERS, Solid-State Sensors, Actuators and Microsystems, 12th International Conference on, 2003  (Volume:2 )

Date of Conference:

8-12 June 2003