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Optimizing Schottky S/D offset for 25-nm dual-gate CMOS performance

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3 Author(s)
Connelly, D. ; Acorn Technol., Palo Alto, CA, USA ; Faulkner, Carl ; Grupp, D.E.

For the first time, mixed mode simulation is used to optimize the design of ultrathin-body dual-gate metal source/drain 25-nm CMOS, showing an advantage for source/drain-to-gate underlap, rather than overlap. The effect of source/drain workfunction and silicon thickness on the optimal underlap, and on the resulting circuit speed, is examined. A substantial performance advantage versus doped source/drain is demonstrated.

Published in:

Electron Device Letters, IEEE  (Volume:24 ,  Issue: 6 )