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This paper presents a digital signal processor (DSP) based device that will digitize a high speed analog signal. The device takes advantage of a new undersampling strategy which employs two clocks, rather than employing a traditional swept delay generator. The random access memory of the DSP and the signal processing capabilities are employed so that the signal is sampled over an integer number of cycles, thus insuring coherency in the sampled data set. Coherency is important property that eliminates additional unwanted discontinuities in a data set which introduces unwanted artifacts in the signal's spectral content. An illustration of the new device is presented in the paper, in addition to laboratory measurements. The results also indicate that the new technique is competitive with solutions that exist in the current literature.