Skip to Main Content
For the last 15 years, Nb-based digital circuits were fabricated with 1-2 kA/cm2 junctions. However, use of high critical current density Nb junctions coupled with state-of-the-art photolithographic tools greatly reduced parasitic capacitance and increase circuit speed. Our 150 mm-wafer integrated circuit process uses 6 kA/cm2 junctions by following a hybrid approach to both optimize wafer throughput and maintain the critical aspects of device fabrication uniformity and reproducibility. Junctions with area less than 0.25 sq.μm are defined using an in-house production electron-beam system. Other process layers not requiring such resolution are defined with an in-house i-line optical stepper allowing line pitch down to 1 μm and layer-to-layer alignment of less than 80 nm. To avoid circuit-limiting parasitic inductance, a chemical mechanical polishing technique is introduced that enables low-inductance 'outside' contacts to our Josephson junctions. In addition, the judicious use of planarization in a fabrication process to decrease circuit inductance are addressed.