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A 4-Gb/s CMOS clock and data recovery circuit using 1/8-rate clock technique

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3 Author(s)
Seong-Jun Song ; Dept. of Electr. Eng. & Comput. Sci., Korea Adv. Inst. of Sci. & Technol., Daejeon, South Korea ; Sung Min Park ; Hoi-Jun Yoo

A 4-Gb/s clock and data recovery (CDR) circuit is realized in a 0.25-μm standard CMOS technology. The CDR circuit exploits 1/8-rate clock technique to facilitate the design of a voltage-controlled oscillator (VCO) and to eliminate the need of 1:4 demultiplexer, thereby achieving low power consumption. The VCO incorporates the ring oscillator configuration with active inductor loads, generating four half-quadrature clocks. The VCO control line comprises both a programmable 6-bit digital coarse control and a folded differential fine control through a charge-pump and a low pass filter. Duty-cycle correction of clock signals is obtained by exploiting a high common-mode rejection ratio differential amplifier at the ring oscillator output. A 1/8-rate linear phase detector accomplishes the phase error detection with no systematic phase offset and inherently performs the 1:4 demultiplexing. Test chips demonstrate the jitter of the recovered clock to be 5.2 ps rms and 47 ps pk-pk for 231-1 pseudorandom bit sequence (PRBS) input data. The phase noise is measured to be -112 dBc/Hz at 1-MHz offset. The measured bit error rate is less than 10-6 for 231-1 PRBS. The chip excluding output buffers dissipates 70 mW from a single 2.5-V supply.

Published in:

Solid-State Circuits, IEEE Journal of  (Volume:38 ,  Issue: 7 )

Date of Publication:

July 2003

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