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We propose a low-voltage micropower (3.6 μW @ 1.1 V, 1 MHz) 16×16 bit asynchronous signed multiplier based on a shift-add structure for an FIR filter for digital hearing instruments. We reduce the power and hardware in several ways. First, we use a sign-magnitude data representation and a maximum of 3 sum of signed power of two terms for the multiplier operand. Second, we truncate the least significant partial products to yield a 16 bit signed product and propose an error correction means to reduce the quantization error. Third, we adopt a low power shifter design and employ our proposed latch adder. Finally, we propose a power efficient speculative delay line to enable the various circuit modules to operate asynchronously. We compare our design against reported designs, and show that our design exhibits the lowest power dissipation and requires a small IC area. We recommend our multiplier for low speed applications (<4 MHz).
Circuits and Systems, 2003. ISCAS '03. Proceedings of the 2003 International Symposium on (Volume:5 )
Date of Conference: 25-28 May 2003