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Design and experimental results of a CMOS flip-flop featuring embedded threshold logic

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3 Author(s)
M. Padure ; Comput. Eng. Lab., Delft Univ. of Technol., Netherlands ; S. Cotofana ; S. Vassiliadis

This paper describes a semi-dynamic CMOS flip-flop family featuring embedded threshold logic functions. First, we present the concept of a flip-flop featuring embedded threshold logic, and then we describe the circuit and its operation. Subsequently, we present the design issues and the experimental results of such threshold logic flip-flops, obtained in 0.25 μm CMOS technology. It is shown in this paper that we successfully manufactured and tested flip-flops having embedded threshold functions with up to 16 data inputs. The proposed flip-flop featuring embedded threshold logic is very suitable for high-performance pipelined arithmetic units since this feature greatly reduces the pipeline overhead, by allowing the elimination of one or more levels of logic from the path leading to the flip-flop.

Published in:

Circuits and Systems, 2003. ISCAS '03. Proceedings of the 2003 International Symposium on  (Volume:5 )

Date of Conference:

25-28 May 2003