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A 3.3 V 1 GHz low-latency pipelined Booth multiplier with new Manchester carry-pass adder

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2 Author(s)
Hwang-Cherng Chow ; Inst. of Semicond. Technol., Chang Gung Univ., Tao-Yuan, Taiwan ; I-Chyn Wey

In this paper, a high speed, low latency pipelined Booth multiplier with new Manchester carry-bypass adder (MCBA) is proposed. By using new partial product generation scheme and new MCBA, the latency is reduced to 6. By using new MCBA, the speed bottleneck is overcome with 40.16% improvement and the energy can be saved with 30.59% improvement. The 13-bit new MCBA pipelined into 2 stages can operate above 1 GHz with worst-case delay of 0.833 ns and consumed only 16.81 mW. Finally, the proposed pipelined Booth multiplier is presented at 3.3 V, 1 GHz in TSMC 0.35 μm process with a power consumption of only 60.18 mW.

Published in:

Circuits and Systems, 2003. ISCAS '03. Proceedings of the 2003 International Symposium on  (Volume:5 )

Date of Conference:

25-28 May 2003