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TestosterICs: a low-cost functional chip tester

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2 Author(s)
D. Harris ; Dept. of Eng., Harvey Mudd Coll., Claremont, CA, USA ; D. Diaz

Students in VLSI design courses find the opportunity to fabricate their chip designs very exciting and motivational. However, testing the chips after fabrication can be a hassle for both students and faculty. In collaboration with Sun Microsystems Laboratories, we have developed a functional chip tester that applies test vectors at low speed to check logical operation. The tester supports packages with up to 256 pins and operates over a range of 1.2-6.5 volts. It reads test vectors directly from IRSIM files and can be programmed through a Java API. The tester can also be used to drive scan chains and other control signals in conjunction with a high-speed signal generator and oscilloscope to test chips at speed. We have released the chip tester plans in open-source form and manufactured 20 units for other universities.

Published in:

Microelectronic Systems Education, 2003. Proceedings. 2003 IEEE International Conference on

Date of Conference:

1-2 June 2003