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Fourteen ways to fool your synchronizer

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1 Author(s)
R. Ginosar ; VLSI Syst. Res. Center, Technion-Israel Inst. of Technol., Haifa, Israel

Transferring data between mutually asynchronous clock domains requires safe synchronization. However, the exact nature of synchronization sometimes eludes designers, and as a result synchronization circuits get "optimized" to the point where they do no longer operate correctly. This paper reviews a number of such cases, analyzes the causes of the errors, and offers a correct synchronizer circuit for each case. A correct two flop synchronizer is presented. After discussing cases that avoid synchronization, the following synchronizers are reviewed: one flop, sneaky path, greedy path, wrong protocol, global reset, async clear, DFT leakage, pulse, slow-to-fast, metastability blocker, parallel and shared flop synchronizers.

Published in:

Asynchronous Circuits and Systems, 2003. Proceedings. Ninth International Symposium on

Date of Conference:

12-15 May 2003