Referenced Items are not available for this document.
A regular (two-flop) synchronizer and six multi-synchronous synchronizers are implemented on a programmable logic device and are measured. An experimental system and method for measuring synchronizers and metastable flip-flops are described. Two separate settling time constants are shown for a metastable flop, confirming earlier results of Dike and Burton [1999]. Clocking cross-talk between asynchronous clocks is demonstrated. The regular synchronizer is useful for communications between asynchronous clock domains, while the other synchronizers can provide higher bandwidth communications between multi-synchronous and mesochronous domains.
Published in:
Asynchronous Circuits and Systems, 2003. Proceedings. Ninth International Symposium on
Date of Conference: 12-15 May 2003
- Page(s):
- 68 - 77
- ISSN :
- 1522-8681
- Print ISBN:
- 0-7695-1898-2
- INSPEC Accession Number:
- 7743483
- Digital Object Identifier :
- 10.1109/ASYNC.2003.1199167
- Product Type:
- Conference Publications
About IEEE Xplore | Contact | Help | Terms of Use | Nondiscrimination Policy | Site Map | Privacy & Opting Out of Cookies
A not-for-profit organization, IEEE is the world's largest professional association for the advancement of technology.
© Copyright 2013 IEEE - All rights reserved. Use of this web site signifies your agreement to the terms and conditions.
