By Topic

Approach to the design of parity-checked arithmetic circuits

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

1 Author(s)
Parhami, B. ; Dept. of Electr. & Comput. Eng., California Univ., Santa Barbara, CA, USA

Achieving fault tolerance via parity checking is attractive due to low overhead in storage and interconnect. However, nonpreservation of parity during arithmetic operations makes it necessary to strip the parity bit before, and to restore it after, such operations. This either leaves the arithmetic part unprotected or else requires complex code conversions. We show that some redundant representations, which are often used for high performance anyway, support a way of designing low-overhead, fault-tolerant arithmetic hardware circuits. An added benefit is localized fault effects due to carry-free arithmetic. Our proposed fault tolerance strategy consists of a way of converting parity-encoded input values to even-parity redundant representations, performing arithmetic with redundant operands in such a way that parity is preserved, and, finally, converting any redundant result to standard parity-encoded output.

Published in:

Signals, Systems and Computers, 2002. Conference Record of the Thirty-Sixth Asilomar Conference on  (Volume:2 )

Date of Conference:

3-6 Nov. 2002