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Parameterisable floating-point operations on FPGA

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2 Author(s)
Lee, B. ; Sch. of Eng., Cardiff Univ., UK ; Burgess, N.

The paper presents a group of IEEE 754-style floating-point units targeted at Xilinx VirtexII FPGA. Special features of the technology are taken advantage of to produce optimised components. Pipelined designs are given that show the latency of /spl sim/100 MHz single-precision components. Non-pipelined reference designs are included for future comparison purposes.

Published in:

Signals, Systems and Computers, 2002. Conference Record of the Thirty-Sixth Asilomar Conference on  (Volume:2 )

Date of Conference:

3-6 Nov. 2002

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