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New graphical IDDQ signatures reduce defect level and yield loss

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3 Author(s)
L. Rao ; Dept. of Electr. & Comput. Eng., Rutgers Univ., Piscataway, NJ, USA ; M. L. Bushnell ; V. D. Agrawal

The measured IDDQ current as a function of vectors is defined here as the IDDQ signature of a chip. We examined the IDDQ signatures of a large number of SEMATECH chips that have been classified as good or bad by a combined decision from functional, delay and scan tests. We find that a single IDDQ threshold, whether absolute or differential, cannot separate good/bad chips with any desirable accuracy, because the good chip signature can be any one of several well-defined graphs. In general, the signature of a good chip is found to contain, discrete levels (or bands) of varying widths and separations. A faulty chip almost always displays noise and glitches in the band structure. Based on observations, we develop a set of five graphical criteria, which provide lower defect level and yield loss compared to other non-IDDQ test methods. The reason is that the graphical procedure customizes the decision for the chip-under-test, and may substantially reduce the usage of other conventional tests.

Published in:

VLSI Design, 2003. Proceedings. 16th International Conference on

Date of Conference:

4-8 Jan. 2003