New graphical I/sub DDQ/ signatures reduce defect level and yield loss

The measured I/sub DDQ/ current as a function of vectors is defined here as the I/sub DDQ/ signature of a chip. We examined the I/sub DDQ/ signatures of a large number of SEMATECH chips that have been classified as good or bad by a combined decision from functional, delay and scan tests. We find that a single I/sub DDQ/ threshold, whether absolute or differential, cannot separate good/bad chips with any desirable accuracy, because the good chip signature can be any one of several well-defined graphs. In general, the signature of a good chip is found to contain, discrete levels (or bands) of varying widths and separations. A faulty chip almost always displays noise and glitches in the band structure. Based on observations, we develop a set of five graphical criteria, which provide lower defect level and yield loss compared to other non-I/sub DDQ/ test methods. The reason is that the graphical procedure customizes the decision for the chip-under-test, and may substantially reduce the usage of other conventional tests.