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Techniques to increase the computational throughput of bit-serial architectures

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3 Author(s)
S. Smith ; University of Edinburgh, Edinburgh, Scotland ; M. McGregor ; P. Denyer

Three architectural techniques are reported, which accelerate bit-serial computation without compromising its favourable advantages. In essence these techniques rely on multi-wire representations of serial data - a step towards bit-parallelism. Interfacing techniques are developed to support the existence of domains of different throughput within a system, thereby enhancing the range of bandwidth-matching techniques available to the systems designer. These techniques also realise the potential to mix processing wordlengths within a serial-data system.

Published in:

Acoustics, Speech, and Signal Processing, IEEE International Conference on ICASSP '87.  (Volume:12 )

Date of Conference:

6-9 April 1987