Skip to Main Content
The architecture and instruction set of a second-generation VLSI digital signal processor are described. This processor represents a significant advance in VLSI digital signal processors. The device may be differentiated from its predecessors by the fact that it more closely resembles a true microprocessor than other DSP microcomputers. Its multiprocessor capabilities further distinguish it, allowing for much more flexibility in overall system design. The architecture of the device allows a dual bus structure to be maintained on-chip, while external bus hardware requirements are minimized via the multiplexing of these busses externally. Some of the notable features incorporated onto the device include two large on-chip RAM blocks, large external program/data address spaces, single-cycle multiply/accumulate instructions, hardware and instructions for efficient memory management, and a versatile multiprocessor interface.
Acoustics, Speech, and Signal Processing, IEEE International Conference on ICASSP '85. (Volume:10 )
Date of Conference: Apr 1985