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SAT and ATPG: Boolean engines for formal hardware verification

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2 Author(s)
Biere, A. ; Dept. of Comput. Sci., Eidgenossische Tech. Hochschule, Zurich, Switzerland ; Kunz, W.

In this survey, we outline basic SAT- and ATPG-procedures as well as their applications in formal hardware verification. We attempt to give a path through the literature and provide a basic orientation concerning the problem formulations and known approaches in this active field of research.

Published in:

Computer Aided Design, 2002. ICCAD 2002. IEEE/ACM International Conference on

Date of Conference:

10-14 Nov. 2002