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Folding of logic functions and its application to look up table compaction

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4 Author(s)
S. Kimura ; System LSI, Waseda Univ., Tokyo, Japan ; T. Horiyama ; M. Nakanishi ; H. Kajihara

This paper describes a folding method for logic functions to reduce the size of memories which are holding the functions. The folding is based on the relation of fractions of logic functions. We show that the fractions of a full adder function have a bit-wise NOT relation and a bit-wise OR relation, and that the memory size becomes half (8-bit). We propose a new 3-1 LUT with folding mechanisms which can implement a full adder with one LUT. A fast carry propagation line is introduced for multi-bit addition. The folding and fast carry propagation mechanisms are shown to be useful in implementing other multi-bit operations and general 4 input functions without extra hardware resources. The paper shows the reduction of the area consumption when using our LUTs compared to the case using 4-1 LUTs on several benchmark circuits.

Published in:

Computer Aided Design, 2002. ICCAD 2002. IEEE/ACM International Conference on

Date of Conference:

10-14 Nov. 2002