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Bit-level scheduling of heterogeneous behavioural specifications

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3 Author(s)
Molina, M.C. ; Dpto. Arquitectura de Computadores y Automatica, Univ. Complutense de Madrid, Spain ; Mendias, J.M. ; Hermida, R.

This paper presents a heuristic scheduling algorithm for heterogeneous specifications, those formed by operations of different types and widths. The algorithm extracts the common operative kernel of the operations, and binds afterwards operations to cycles with the aim of distributing uniformly the number of bits calculated per cycle. In consequence, operations may be fragmented and executed during a set of non-necessarily consecutive cycles, and over a set of several linked simple hardware resources. The proposed algorithm, in combination with allocation algorithms able to guarantee bit-level reuse of hardware resources, obtains considerably smaller datapaths than the ones proposed by conventional synthesis algorithms. In the datapaths produced, the type, number, and width of the hardware resources are independent of the type, number, and width of the specification operations and variables.

Published in:

Computer Aided Design, 2002. ICCAD 2002. IEEE/ACM International Conference on

Date of Conference:

10-14 Nov. 2002