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Power efficiency of voltage scaling in multiple clock multiple voltage cores

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2 Author(s)
A. Iyer ; Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA ; D. Marculescu

Due to increasing clock speeds, increasing design sues and shrinking technologies, it is becoming more and more challenging to distribute a single global clock throughout a chip. In this paper we study the effect of using a Globally Asynchronous Locally Synchronous (GALS) organization for a superscalar out-of-order processor, both in terms of power and performance. To this end, we propose a novel modeling and simulation environment for multiple clock cores with static or dynamically variable voltages for each synchronous block Using this design exploration environment we were able to assess the power/performance tradeoffs available for Multiple Clock Single Voltage (MCSV), as well as Multiple Clock Dynamic Voltage (MCDV) cores. Our results show that MCSV processors are 10% more power efficient when compared to single-clock single voltage designs with a performance penalty of about 10% By exploiting the flexibility of independent dynamic voltage scaling the various clock domains, the power efficiency of GALS designs can be improved by 12% on average, and up to 20% more in select cases. The power efficiency of MCDV cores becomes comparable with the one of Single Cloak Dynamic Voltage (SCDV) cores while being up to 8% better in some cases. Our results show that MCDV cones consume 22% less power at an average 12% performance loss.

Published in:

Computer Aided Design, 2002. ICCAD 2002. IEEE/ACM International Conference on

Date of Conference:

10-14 Nov. 2002