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On-chip interconnect modeling by wire duplication

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3 Author(s)
Guoan Zhong ; Sch. of Electr. & Comput. Eng., Purdue Univ., West Lafayette, IN, USA ; Cheng-Kok Koh ; Roy, K.

In this paper, we present a novel wire duplication-based interconnect modeling technique. The proposed modeling technique exploits the sparsity of the L-1 matrix, where L is the inductance matrix, and constructs a sparse and stable equivalent RLC circuit by windowing the original inductance matrix. The model avoids matrix inversions. Most important, it is more accurate and more efficient than many existing techniques.

Published in:

Computer Aided Design, 2002. ICCAD 2002. IEEE/ACM International Conference on

Date of Conference:

10-14 Nov. 2002