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Minimizing power across multiple technology and design levels

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1 Author(s)
T. Sakurai ; Center for Collaborative Res. & Inst. of Ind. Sci., Tokyo Univ., Japan

Approaches to achieve low power and high-speed VLSIs are described with the emphasis on techniques across multiple technology and design levels. To suppress the leakage current in a standby mode, boosted gate MOS (BGMOS) is effective, which is based on cooperation between technology level and circuit level. To reduce the power in an active mode, VDD-hopping and VTH-hopping are promising, which are cooperative approaches between circuit and software. Power consumed in the interconnect system can be reduced by a cooperative approach between application and layout as in bus shuffling. Other low-power design approaches are also discussed.

Published in:

Computer Aided Design, 2002. ICCAD 2002. IEEE/ACM International Conference on

Date of Conference:

10-14 Nov. 2002