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An NMOS voltage reference

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4 Author(s)
R. Blauschild ; Signetics Corp., Sunnyvale, CA, USA ; P. Tucci ; R. Muller ; R. Meyer

An NMOS temperature-stable voltage reference, affording - in breadboard results - a temperature drift of less than 6 PPM/°C, will be described. Calculations show that less than 2 PPM/°C can be achieved with proper choice of device geometries.

Published in:

Solid-State Circuits Conference. Digest of Technical Papers. 1978 IEEE International  (Volume:XXI )

Date of Conference:

15-17 Feb. 1978