A parallel pattern mixed-level fault simulator

A parallel pattern mixed-level fault simulator is described and demonstrated. The switch level allows the simulator to treat transistor faults such as stuck-open and stuck-short faults, the gate level allows the simulator to conserve the speed advantage of the gate level simulation, and the parallel pattern single-fault propagation (PPSFP) strategy enhances the simulation speed at least one order of magnitude, depending on the word length to implement the simulator. The simulator is built on the basis of a set of operators that translate the switch-level signal propagation into Boolean operations and transform the gate-level logic elements into symbolic logic representations. These make parallel pattern evaluation for switch level simulation possible. The implemented simulator exhibits an O(G/sup 1.88/) performance for the logic-level simulation. This can be further improved if a longer word length is adopted.<
>