Cart (Loading....) | Create Account
Close category search window
 

Multilevel synthesis minimizing the routing factor

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

4 Author(s)
Abouzeid, P. ; Inst. Nat. Polytech. de Grenoble/CSI, France ; Sakouti, K. ; Saucier, G. ; Poirot, F.

A multilevel logic synthesis method based on standard cells and aiming at reducing both gate and wiring areas is presented. The goal is to decrease the routing factor which is defined as a ratio between the routing area and the gate area. The wiring is taken into account during the synthesis steps (factorization and technology mapping). The approach is based on a lexicographical expression of a Boolean function controlling the input dependency and on a kernel filtering controlling the excessive factorizations responsible for wiring complexity increase

Published in:

Design Automation Conference, 1990. Proceedings., 27th ACM/IEEE

Date of Conference:

24-28 Jun 1990

Need Help?


IEEE Advancing Technology for Humanity About IEEE Xplore | Contact | Help | Terms of Use | Nondiscrimination Policy | Site Map | Privacy & Opting Out of Cookies

A not-for-profit organization, IEEE is the world's largest professional association for the advancement of technology.
© Copyright 2014 IEEE - All rights reserved. Use of this web site signifies your agreement to the terms and conditions.