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Surface trapping has been identified as a mechanism for lower than expected output power for experimental AlGaN/GaN HEMTs devices. This paper presents dynamic loadline analysis as a means of understanding device behavior that limits large signal performance. From observations of measured data, a model for bias-dependent drain resistance caused by trap-induced space-charge in the ungated region on the drain side of the gate is proposed. This bias-dependent drain resistance model is implemented in conjunction with a Curtice-cubic analytical transistor model to simulate the observed behavior.