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The issues involved in the thermal management of 2-5-W very large-scale integrated (VLSI) chips applied in cost driven systems is addressed. Applying presently available ceramic packages and metal heatsinks to form a new packaging scheme requires caution to avoid long-term reliability failures due to thermal stresses. This is especially true when using ceramic lids with frit seals. This problem and some possible solutions are discussed in detail. For lead counts over 84 a trend exists toward pin-grid package designs. The thermal performance test results for a couple of representative pin-grid package types will he reviewed. These results show that this style of package has good thermal characteristics. The effect on thermal performance of die size variations is also discussed.