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Application of Parylene for protecting microelectronic circuits from loose particles and external environment has been visualized for many years. With a joint effort by NASA and TMD, a process has now been qualified to perform Parylene deposition on hybrid circuits on a production basis, for the Centaur inertial guidance computer. The Parylene coating process developed during this program consists of a) obtaining a hybrid cover with a hole in it, b) sealing of the circuit with a hole in the cover, c) Parylene coating through the hole with the external leads protected from Parylene by appropriate fixturing, and d) sealing of the hole by soldering a pretinned Kovax tab. Development of the above process required optimization of the Parylene coater parameters to obtain a uniform consistent coating which could offer adequate protection to the circuits, fixture design for packages of various types, determination of the size of the deposition hole, the amount of dimer charge per run, a process to hermetically seal the deposition holes and establishment of quality control techniques or acceptance criteria for the deposited film. Several experimental runs were made on test circuits as well as actual production circuits to determine the effect of Parylene coating on active components, thin film resistors, and wire bonds under various conditions. Tests were also made to determine if Parylene indeed protected circuits from loose particles and external environment. After these experiments, Parylene coating acceptance standards were established and a long and rigorous qualification program was completed in order to prove the feasibility of this process. The results of the qualification program will be reported in a future publication. It is concluded that Parylene offers excellent protection against loose particles and a degree of protection from some environmental conditions. It is expected that the fraction of hybrids being coated with Parylene will continue to increase in the microelectronic industry.