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Statistical bin limits: an approach to wafer dispositioning in IC fabrication

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2 Author(s)
Illyes, S. ; Intel Corp., Rio Rancho, NM, USA ; Baglee, D.

The methodology of selecting and implementing statistical bin limits (SBLs) for wafer-level testing is discussed. Improvements in the manufacturing flow are discussed. It is found that SBLs can detect process shifts, reject misprocessed material, aid in the streamlining of packaged units, and increase the cost effectiveness of these units. It is shown that the methodology does not add to the complexity of the sort flow. Implementation and maintenance are straightforward and simple

Published in:

Advanced Semiconductor Manufacturing Conference and Workshop, 1990. ASMC 90 Proceedings. IEEE/SEMI 1990

Date of Conference:

11-12 Sep 1990

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