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A 1.2 GHz high-speed 256-bit shift register LSI

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7 Author(s)
H. Mori ; OKI Electr. Ind. Co. Ltd., Tokyo, Japan ; A. Tsukuda ; H. Nishimura ; M. Takada
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The authors have developed a high-speed 256-bit shift register LSI intended for use in gigabit-rate signal storage applications in GaAs MESFET DCFL/SBFL (direct-coupled FET logic/superbuffer FET logic) circuits. This shift register has serial data input and serial data output composition, suitable for line memory usage. To attain both high-speed and low power characteristics, the authors used a serial-input-data to parallel-internal-data and parallel-internal-data to serial-output-data conversion system. The maximum clock rate under which this device can operate is 1.2 GHz. It has a low (1.2-W) power consumption from a single 2-V power supply.<>

Published in:

Gallium Arsenide Integrated Circuit (GaAs IC) Symposium, 1988. Technical Digest 1988., 10th Annual IEEE

Date of Conference:

6-9 Nov. 1988